Field of the Invention
This invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device including MOS transistors, which is capable of operating at a low power supply voltage when taken active and reducing power consumption resultant from a leakage current during standby.
Description of the Related Art
As high integration of an LSI or an increase in performance thereof progresses, how to reduce the power consumption has recently been recognized as an important problem. It can be said that in a CMOS type LSI in particular, a reduction in the power supply voltage is a method most effective for low power consumption because the power consumption is directly proportional to the square of the power supply voltage. However, the reduction in the power supply voltage will cause a reduction in the operating speed of a MOS transistor. Avoiding this needs to reduce a threshold voltage when it is active. However, the reduction in the threshold voltage leads to an increase in leakage current of the MOS transistor during standby. An MTCMOS (Multithreshold-Voltage CMOS) has been proposed as an LSI for solving such a problem. The MTCMOS has been introduced in the paper: .left brkt-top.1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS (IEEE JOURNAL OF SOLID-STATE CIRCUIT. VOL. 30. NO. 8, AUGUST 1995 ) or the like, for example.
This type of MTCMOS generally has at least one logic circuit electrically connected between a virtual power supply line and a virtual power supply line and comprised of MOS transistors each having a low threshold voltage and standby power control MOS transistors each having a high threshold voltage, which are electrically connected between a power supply line and the virtual power supply line and between a ground line and a virtual ground line to reduce the leakage current of each MOS transistor during standby. Further, MTCMOS has a latch circuit directly connected between the-power supply line and the ground line. Since the latch circuit is provided with MOS transistors each having a high threshold voltage, which are directly connected to the power supply line and the ground line, it is possible to prevent the destruction of data stored in the logic circuit even if the virtual power supply line and the virtual ground line are respectively brought to a floating state during standby.
However, the conventional MTCMOS adopts a standard cell system in which layout design is performed in units of a latch circuit such as a flip-flop circuit comprised of an inverter circuit, a master circuit and a slave circuit, and a logic circuit. The layout design based on such a standard cell system has a problem in that since it is performed in respective circuit units, the period required to manufacture the MTCMOS becomes long.
In the conventional MTCMOS on the other hand, the threshold voltage of the standby power control MOS transistor used to reduce the leakage current flowing during standby is set sufficiently high. Thus, when it is taken active, a sufficient current is not supplied to the virtual power supply line or the virtual ground line thereby to make the voltage value unstable. As a result, the conventional MTCMOS has inconvenience that a high-speed logical operation cannot be implemented.